1. Field of the Invention
The present invention relates to microcomputers, having a central processing unit (hereinafter referred to as "CPU"), a random access memory (hereinafter referred to as "RAM") and an internal data bus through which various data is transferred between the CPU and the RAM. More specifically, the present invention relates to such microcomputers capable of reading a data out of a memory location of the RAM designated by a RAM address signal supplied by the CPU and writing the read out data to a different memory location of the RAM designated by another RAM address signal similarly supplied by the CPU.
2. Description of the related art
Conventionally, typical microcomputers capable of transferring data between different memory locations include a CPU, a data bus coupled to the CPU, and a RAM receiving an address signal from the CPU. A first read/write unit is coupled between the RAM and the data bus. The CPU supplies a first read signal and a first write signal to the first read/write unit, so as to control the operation of the first read/write unit.
The microcomputer further includes a register to store a data temporarily, and a second read/write unit coupled between the register and the data bus. The CPU supplies a second read signal and a second write signal to the second read/write unit.
A microcomputer constructed as mentioned above operates in the following manner.
The CPU supplies a read address signal to the RAM. The first read/write unit reads a data out of the RAM at the address designated by the above read address signal and then outputs the data onto the data bus in response to the first read signal. The second read/write unit writes the data on the data bus to the register in response to the second write signal. Such a bus cycle is called a RAM read cycle.
After the RAM read cycle, the CPU supplies a write address signal to the RAM. The second read/write unit reads the data stored in the register and outputs the data onto the data bus in response to the second read signal. The first read/write unit writes the data on the data bus to the RAM at the address designated by the write address signal. Such a bus cycle is called a RAM write cycle.
Such a data transfer within the same RAM is required in the field of various digital signal processings including an image processing, a voice processing, etc.
In conventional microcomputers, a RAM disposed on a microcomputer chip with a CPU are functions:
(1) to store a data to be treated in the CPU and a data treated in the CPU, and
(2) to store a data inputted from and a data to be outputted to the outside of the microcomputer.
An internal data bus must be, therefore, necessarily used every time any instructions to access the RAM such as a memory read instruction and a memory write instruction are executed. Bus cycle is scheduled in such a manner that the internal data bus may be assigned to reading a data out of or writing a data to the RAM in case of executing a RAM access instruction. Namely, it is necessary to control the internal bus so that during the period the data is transferred between two units through the internal data bus the other units are not allowed to access the internal data bus. To make the above control simple, a RAM is coupled directly to an internal bus similarly with other units of a CPU.
With the conventional microcomputer, a data at the address designated by a read address signal is written at the different address designated by a write address signal by means of the operation as described above. Namely, in case of transferring a data at the address A of the RAM to the address B inside the same RAM, a read instruction for a data at the address A and a write instruction for writing the data at the address B have to be executed. Since these read and write instructions are independent of each other, it is required to store the data which is read out of the address A and outputted onto the data bus by a read instruction somewhere appropriate until the write instruction is sequentially executed. This is why a register is provided being coupled to the data bus. The data read out of the address A is temporarily stored in the register when the read instruction is executed and the stored data is written to the address B through the data bus when the write instruction is executed.
In the conventional microcomputer as mentioned above, a register is coupled to a RAM through a data bus. The data bus is, therefore, used during both a RAM read cycle and a RAM write cycle in case of transferring a data from an address to a different address of the same RAM. Consequently, any instructions which require to use a data bus may not be executed during these two bus cycles.